module enqueueMuxerSpecial (
    input wire clk,
    input wire rst,
    input wire [15:0] enqueue_sucess,
    input wire [15:0] enqueue_ack,
    input wire [15:0] enqueue_en_in,
    input wire [5:0] enqueue_priority_in [0:15],
    input wire [9:0] enqueue_value_in [0:15],
    output reg [15:0] enqueue_en_out,
    output reg [5:0] enqueue_priority_out [0:15],
    output reg [15:0] enqueue_value_out [0:15]
);
    integer i;

    always @(posedge clk) begin
        if (rst) begin
            enqueue_en_out <= 16'h0000;
            for (i=0; i<16; i=i+1) begin
                enqueue_priority_out[i] <= 0;
                enqueue_value_out[i] <= 0;
            end
        end
        else begin
            for (i=0; i<16; i=i+1) begin
                if (enqueue_ack[i] && enqueue_sucess[i]) begin
                    enqueue_en_out[i] <= 0;
                    enqueue_priority_out[i] <= 0;
                end
                else begin
                    if (enqueue_en_in[i]) begin
                        enqueue_en_out[i] <= 1;
                        enqueue_priority_out[i] <= enqueue_priority_in[i];
                        enqueue_value_out[i] <= (i<<10)+enqueue_value_in[i];
                    end
                    else begin
                        enqueue_en_out[i] <= 0;
                    end
                end
            end
        end
    end
    
endmodule